As electronic products continue to decrease in size in order to deliver more and more features and performance in smaller and smaller packages, the feature sizes of the electronic devices employed by such products, naturally, decrease. When metal oxide semiconductor (MOS) transistors decrease in size, their gate length and channel length below the gate decrease, and, unfortunately, their operating characteristics may deteriorate due to, for example, reduced capacitance between the gate and channel.
One approach to improving the performance of a MOS device, while, at the same time, reducing feature sizes, is to substitute a material having a high dielectric constant for the more conventional silicon oxide layer used for gate insulation in order to reduce leakage current between a device's gate electrode and channel region. Additionally, because the polysilicon generally used as a gate electrode material has a relatively high resistance, metal electrodes may be used instead of polysilicon electrodes.
Multi gate transistors employing a three-dimensional (3D) channel may also be employed in order to increase device density. Such a device may form a fin or a nanowire-shaped silicon body on a substrate, with a gate on a surface of the silicon body has, for example. Such devices may afford improved current control and suppression of short channel effect (SCE), for example.